1. Field of the Invention
The present invention relates to a method of extending an input signal range of a component that receives the input signal. Specifically, the present invention relates to a design for an amplifier that extends its input signal range. More specifically, the present invention relates to a design for a differential amplifier with a large input common mode signal range.
2. Background Art
Operational amplifiers are key elements used in many analog and mixed analog/digital applications. Increasingly, these applications are being realized in smaller, portable packages, which require low power supply voltages. This necessity taxes the ability of operational amplifiers to provide the large voltage swings needed to ensure a wide dynamic range.
Conventionally, operational amplifiers are implemented using differential amplifiers to increase the voltage swing. The purpose of a differential amplifier is to sense changes in its differential input signal while rejecting changes in its common mode, or average, input signal. By removing the common mode component of an input signal, differential amplifiers can support relatively large voltage swings.
Differential amplifiers are essential building blocks of most modern IC amplifiers and are predicated on the ability to fabricate matched transistors on a chip. Differential amplifiers are particularly useful for mixed signal applications where noise generated by digital circuits can distort analog signals. Noise appearing on both input signals of a differential circuit is rejected at the output signals.
FIG. 1 is a schematic diagram of a conventional differential amplifier 100. Differential amplifier 100 comprises two transistors “M1” 102 and “M2” 104 with source terminals connected together. A current source “ITAIL” 106 is connected in parallel with a resistor “RTAIL” 108 between the source terminals and a first power supply voltage “VSS” 110. (In an embodiment, VSS 110 could be analog ground.) A resistor is connected to the drain terminal of each transistor. “RD1” 112 is connected to the drain terminal of M1 102; “RD2” 114 is connected to the drain terminal of M2 104. RD1 112 and RD2 114 are together connected to a second power supply voltage “VDD” 116. (In an embodiment, VDD 116 could be analog ground.) Differential amplifier 100 receives a differential input signal and produces a differential output signal.
The differential input signal comprises a first input signal “vi1” 118, which is applied to the gate terminal of M1 102, and a second input signal “vi2” 120, which is applied to the gate terminal of M2 104. The differential output signal comprises a first output signal “vo1” 122, which is produced at the drain terminal of M2 104, and a second output signal “vo2” 124, which is produced at the drain terminal of M1 102. Preferably, differential amplifier 100 is balanced such that each component on the side of one output (e.g., M1 102, RD1 112) corresponds to an identical component on the side of the other output (e.g., M2 104, RD2 114).
M1 102 and M2 104 comprise a differential pair and act to control the distribution of current flowing from ITAIL 106 between VDD 116 and VSS 110. The sum of the current flowing through both M1 102 and M2 104 equals ITAIL 106. So, for example, as vi1 118 rises with respect to vi2 120, the portion of the total current of ITAIL 106 that flows through M1 102 and RD1 112 increases, while the portion that flows through M2 104 and RD2 114 decreases. More current flowing through RD1 112 increases the drop in voltage across RD1 112, while less current flowing through RD2 114 decreases the drop in voltage across RD2 114. Thus, vo1 122 rises with respect to vo2 124.
The differential input signal can be expressed as shown in Eq. (1):vid=vi1−vi2,  Eq. (1)while the common mode input signal can be expressed as shown in Eq. (2):vic=[vi1+vi2]/2.  Eq. (2)Likewise, the differential output signal can be expressed as shown in Eq. (3):vod=vo1−vo2,  Eq. (3)while the common mode output signal can be expressed as shown in Eq. (4):voc=[vo1+vo2]/2.  Eq. (4)
As noted above, the purpose of differential amplifier 100 is to sense changes in its differential input signal Vid while rejecting changes in its common mode input signal vic. The ability of differential amplifier 100 to realize this goal can be expressed by several figures of merit. Particularly, the common mode rejection ratio, CMRR, is defined as shown in Eq. (5):CMRR≡|Adm/Acm|,  Eq. (5)where Adm is the differential mode gain and Acm is the common mode gain. Adm can be expressed as shown in Eq. (6):Adm=vod/vid|vic=0=½{[(vo1−vo2)/vi1]+[(vo2−vo1)/vi2]}.  Eq. (6)Acm can be expressed as shown in Eq. (7):Acm=voc/vic|vid=0=½{[(vo1+vo2)/vi1]+[(vo2+vo1)/vi2]}.  Eq. (7)
In designing differential amplifiers, it is desired to maximize the value of CMRR. This is indicative of maximizing the desired differential mode gain and/or minimizing the undesired common mode gain. Small signal analysis of a differential amplifier can be used to express CMRR as a function of the physical parameters internal to the transistors from which differential amplifier 100 is comprised. The small signal analysis needs to account for both differential mode and common mode operations.
FIG. 2 is a schematic diagram of a small signal model circuit 200 of differential amplifier 100. In circuit 200, M1 102 is modeled as a current source “i1” 202 connected in parallel with an output resistance “ro1” 204 between a node “N0” 206 and a node “N1” 208. An input resistance “rπ1” 210 is connected in series between N0 206 and a first input signal “vi3” 212. RD1 112 is connected in series between N1 208 and ground. A first output signal “vo3” 214 is produced at N1 208. Likewise, M2 104 is modeled as a current source “i2” 216 connected in parallel with an output resistance “ro2” 218 between N0 206 and a node “N2” 220. An input resistance “rπ2” 222 is connected in series between N0 206 and a second input signal “vi4” 224. A second output signal “vo4” 226 is produced at N2 220. RD2 114 is connected in series between N2 220 and ground. RTAIL 108 is connected in series between N0 206 and ground.
The value of i1 202 can be expressed as shown in Eq. (8):i1=gmv1,  Eq. (8)where gm is the transconductance of M1 102 (or M2 104, because differential amplifier 100 is balanced), and v1 is the voltage drop across rπ1 210. Likewise, the value of i2 216 can be expressed as shown in Eq. (9):i2=gmv2,  Eq. (9)where v2 is the voltage drop across rπ2 222.
In differential mode, the value of vi3 212 can be expressed as shown in Eq. (10):vi3=vid/2,  Eq. (10)while the value of vi4 224 can be expressed as shown in Eq. (11):vi4=−vid/2.  Eq. (11)Likewise, the value of vo3 214 can be expressed as shown in Eq. (12):vo3=vod/2,  Eq. (12)while the value of vo4 226 can be expressed as shown in Eq. (13):vo4=−vod/2.  Eq. (13)
Where M1 102 and M2 104 are MOSFETs, input resistances rπ1 210 and rπ2 222 are sufficiently large as to be considered infinite. Thus, the value of i1 202 can be expressed as shown in Eq. (14):i1=gmvid/2,  Eq. (14)and the value of i2 216 can be expressed as shown in Eq. (15):i2=−gmvid/2.  Eq. (15)
Because differential amplifier 100 is balanced and the input signals are driven by equal but opposite voltages, there is no variation in the voltage across RTAIL 108. In small signal analysis, this condition is effectively the same as connecting N0 206 to ground. Therefore, further analysis of small signal model circuit 200 operating in differential mode can be simplified by analyzing a small signal differential mode model half circuit.
FIG. 3 is a schematic diagram of a small signal differential mode model half circuit 300. In half circuit 300, i1 202, ro1 204, and RD1 112 are connected in parallel between N0 206 and N1 208. N0 206 is connected to ground. vo3 214 is produced at N1 208. Recalling Eqs. (6), (12), and (14), Adm can be expressed as shown in Eq. (16):Adm=−gmR,  Eq. (16)where R is the effective resistance of the parallel combination of ro1 204 and RD1 112.
Returning to FIG. 2, in common mode, the values of vi3 212 and vi4 224 can be expressed as shown in Eq. (17):vi3=vi4=vic.  Eq. (17)Likewise, the values of vo3 214 and vo4 226 can be expressed as shown in Eq. (18):vo3=vo4=voc.  Eq. (18)
Where M1 102 and M2 104 are MOSFETs, input resistances rπ1 210 and rπ2 222 are sufficiently large as to be considered infinite. Thus, the values of i1 202 and i2 216 can be expressed as shown in Eq. (19):i1=i2=gmvic.  Eq. (19)
Because differential amplifier 100 is balanced and the input signals are driven by equal voltages, further analysis of small signal model circuit 200 operating in common mode can be simplified by analyzing a small signal common mode model half circuit.
FIG. 4 is a schematic diagram of a small signal common mode model half circuit 400. In half circuit 400, a resistor “RTAIL2” 402 is connected between N0 206 and ground. The value of RTAIL2 402 can be expressed as shown in Eq. (20):RTAIL2=2×RTAIL.  Eq. (20)Conceptually, RTAIL 108 in small signal model circuit 200 is first modeled as a parallel combination of two resistors connected between N0 206 and ground. Each resistor in the parallel combination has a resistance value equal to RTAIL2 402, such that the resistance value of the parallel combination remains equal to RTAIL 108. This enables small signal model circuit 200 to be reconfigured as small signal common mode model half circuit 400 so that it accounts for the voltage drop across RTAIL 108.
Also in half circuit 400, i1 202 is connected between N0 206 and N1 208 so that i1 202 and RTAIL2 402 are connected in series between N1 208 and ground. Additionally, ro1 204 and RD1 112 are connected in parallel between N1 208 and ground. vo3 214 is produced at N1 208. Recalling Eqs. (7), (18), (19), and (20), Acm can be expressed as shown in Eq. (21):Acm=−gmR/[1+gmRTAIL2],  Eq. (21)where R is the effective resistance of the parallel combination of ro1 204 and RD1 112.
Thus, recalling Eqs. (5), (16), and (21), CMRR, as a function of the physical parameters internal to the transistors from which differential amplifier 100 is comprised, can be expressed as shown in Eq. (22):CMRR=1+gmRTAIL2.  Eq. (22)
In practical implementations, differential amplifiers are realized using active devices for current sources, and in most cases also for loads. Active devices provide large values of resistance, while dropping less voltage and consuming less die area than passive resistors.
FIG. 5 is a schematic diagram of a conventional differential amplifier 500 with active loads. Differential amplifier 500 comprises a differential pair 502 of amplifying transistors M1 102 and M2 104 with source terminals connected together. A load transistor is connected to the drain terminal of each amplifying transistor. “M3” 504 is connected to the drain terminal of M1 102; “M4” 506 is connected to the drain terminal of M2 104. M3 504 and M4 506 are together connected to power supply voltage VDD 116. A first bias voltage “Vbiasp” 508 holds load transistors M3 504 and M4 506 in saturation. A fifth transistor “M5” 510 provides a current source for differential amplifier 500. M5 510 is connected between the source terminals of M1 102 and M2 104, and power supply voltage VSS 110. A second bias voltage “Vbiasn” 512 holds transistor M5 510 in saturation. First input signal vi1 118 is applied to the gate terminal of M1 102 and first output signal vo1 122 is produced at the drain terminal of M2 104. Second input signal vi2 120 is applied to the gate terminal of M2 104 and second output signal vo2 124 is produced at the drain terminal of M1 102.
In differential amplifier 500, M1 102, M2 104, and M5 510 are NMOSFETs, while M3 504 and M4 506 are PMOSFETs. However, one skilled in the art would recognize that other transistor configurations could also be used. Preferably, differential amplifier 500 is balanced such that each component on the side of one output (e.g., M1 102, M3 504) corresponds to an identical component on the side of the other output (e.g., M2 104, M4 506).
Unfortunately, while the use of active devices for current sources and loads has several advantages, it also presents the problem of limiting the input common mode signal range. (It is desirable to have the input common mode signal range from VSS to VDD.) This is due to the need to hold current source transistors in saturation. This common mode confinement is particularly difficult in applications seeking to meet, for example, IEEE Std 1596.3-1996 for Low-Voltage Differential Signals for Scalable Coherent Interface, which requires a large input common mode signal range. An analysis of the input common mode signal range for differential amplifier 500 highlights this limitation.
For differential amplifier 500, the lower limit of vic can be expressed as shown in Eq. (23):vic>VSS+vTn+vovM5,  Eq. (23)where vTn is the threshold voltage of M1 102 (or M2 104), and vovM5 is the overdrive voltage of M5 510.
Likewise, the upper limit of vic can be expressed as shown in Eq. (24):vic<VDD+vTn−vovload,  Eq. (24)where vovload is the overdrive voltage of M3 504 (or M4 506). Normally, vTn>vovload. Thus, the analysis shows that, while the upper limit of the input common mode signal range desirably can be maintained greater than or equal to VDD, the lower limit of the input common mode signal range undesirably often must be greater than VSS.
Conventionally, this problem has been addressed by configuring a differential amplifier to have two differential pairs to increase the input common mode signal range. FIG. 6 is a schematic diagram of a conventional differential amplifier 600 with two differential pairs. Differential amplifier 600 comprises differential pair 502 of amplifying transistors M1 102 and M2 104 with source terminals connected together. M5 510 is connected between VSS 110 and the source terminals of M1 102 and M2 104. Vbiasn 512 holds transistor M5 510 in saturation.
Differential amplifier 600 further comprises a second differential pair 602 of amplifying transistors “M6” 604 and “M7” 606 with source terminals connected together. A sixth transistor “M8” 608 provides a current source for amplifying transistors M6 604 and M7 606. M8 608 is connected between VDD 116 and the source terminals M6 604 and M7 606. A third bias voltage “Vbiasp2” 610 holds transistor M8 608 in saturation.
First input signal vi1 118 is applied to the gate terminals of both M1 102 and M6 604. Second input signal vi2 120 is applied to the gate terminals of both M2 104 and M7 606. First output signal vo1 122 is produced at the drain terminal of M2 104. Second output signal vo2 124 is produced at the drain terminal of M1 102. A third output signal “vo5” 612 is produced at the drain terminal of M7 606. A fourth output signal “vo6” 614 is produced at the drain terminal of M6 604.
Differential amplifier 600 requires a subsequent stage, usually a cascode structure, to provide loads for amplifying transistors M1 102, M2 104, M6 604, and M7 606, and to process the four output signals vo1 122, vo2 124, vo5 612, and vo6 614.
In differential amplifier 600, M1 102, M2 104, and M5 510 are NMOSFETs, while M6 604, M7 606, and M8 608 are PMOSFETs. However, one skilled in the art would recognize that other transistor configurations could also be used. Preferably, differential amplifier 600 is balanced such that each component on the side of one output (e.g., M1 102, M6 604) corresponds to an identical component on the side of the other output (e.g., M2 104, M7 606).
An analysis of the input common mode signal range for differential amplifier 600 shows that it is wider than that of differential amplifier 500. For differential amplifier 600, the lower limit of vic can be expressed as shown in Eq. (25):vic>VSS+vTp+vovloadn,  Eq. (25)where vTp is the threshold voltage of M6 604 (or M7 606), and vovloadn is the overdrive voltage of a NMOSFET load in the subsequent stage (not shown). Normally, vTp<0, but|vTp|>|vovloadn|.
Likewise, the upper limit of Vic can be expressed as shown in Eq. (26):vic<VDD+vTn−vovloadp,  Eq. (26)where vovloadp is the overdrive voltage of a PMOSFET load in the subsequent stage (not shown). Thus, when vovloadn=vovM5 and vovloadp=vovload, comparisons of Eq. (23) with Eq. (25), and Eq. (24) with Eq. (26) show that the upper limit of the input common mode signal range desirably can be maintained greater than or equal to VDD, and the lower limit of the input common mode signal range desirably can also be maintained less than or equal to VSS.
However, while differential amplifier 600 maximizes the input common mode signal range, the design presents several problems that detract from its usefulness. Significant power is dissipated and valuable substrate area is consumed to support the second current source transistor and to support the subsequent stage needed to provide loads for the amplifying transistors and to process the two additional output signals. Also, successful implementation of differential amplifier 600 depends on an ability to fabricate differential pairs 502 and 602 with matching gains and similar transient behaviors. This is very difficult to realize when differential pair 502 comprises NMOSFETs and differential pair 602 comprises PMOSFETs.
What is needed is a differential amplifier design that optimizes the input common mode signal range, power dissipated, and substrate area consumed, and avoids the difficulty of matching gains between a differential pair of NMOSFETs and a differential pair of PMOSFETs.